HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 502

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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13.3.5
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and
CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13.5 shows
some sample bit rates.
If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate
is output from the SCK pin.
Where: N = Value set in BRR (0 N 255)
Table 13.4 Correspondence between n and CKS1, CKS0
n
0
1
2
3
Table 13.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0)
N
0
1
2
Note: Bit rates are rounded to the nearest whole number.
488
B = Bit rate (bit/s)
ø = Operating frequency (MHz)
n = See table 13.4
B =
Clock
1488
CKS1
0
1
10.00
13441
6720
4480
2
2n–1
10.714
14400
7200
4800
(N + 1)
CKS0
0
1
0
1
13.00
17473
8737
5824
10
6
14.285
19200
9600
6400
ø (MHz)
16.00
21505
10753
7168
18.00
24194
12097
8065
20.00
26882
13441
8961

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