HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 192
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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7.1.2
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information and hence helping to increase processing speed.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
174
Interrupt
request
Block Diagram
Legend
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERE
DTVECR
Interrupt controller
CPU interrupt
request
Figure 7.1 Block Diagram of DTC
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to E
: DTC vector register
DTC
Internal address bus
Internal data bus
On-chip
RAM
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