HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 188
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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6.7.4
Figure 6.19 shows the timing for transition to the bus-released state.
Address bus
HWR, LWR
[1]
[2]
[3]
[4]
[5]
Data bus
BREQ
BACK
Transition Timing
RD
AS
ø
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Figure 6.19 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
External bus released state
[3]
2
state.
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
cycle
CPU
169
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