HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 485

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Thus the reception margin in asynchronous mode is given by formula (1) below.
Where M : Reception margin (%)
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
M = (0.5 –
M = (0.5 –
= 46.875%
Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode
0
2
2N
1
1
8 clocks
Start bit
16
) – (L – 0.5) F –
)
100%
16 clocks
7
D – 0.5
N
15 0
(1 + F)
D0
100%
. . . . . . . . Formula (1)
. . . . . . . . Formula (2)
7
15 0
D1
471