MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 73

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68H(R)C908JL3
MOTOROLA
Signal Name
PIN LOGIC
2OSCOUT
OSCOUT
PORRST
RESET
IRST
INTERNAL
R/W
IDB
IAB
PULL-UP
—
VDD
Rev. 1.0
Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit.
The 2OSCOUT frequency divided by two. This signal is again divided by two in the
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4)
SIM RESET STATUS REGISTER
RESET PIN CONTROL
POR CONTROL
Table 7-1. Signal Name Conventions
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
INTERRUPT CONTROL
CLOCK
System Integration Module (SIM)
CLOCK GENERATORS
RESET
COUNTER
SIM
2
CONTROL
MASTER
RESET
Description
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
2OSCOUT (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
System Integration Module (SIM)
Technical Data
Introduction
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