MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 180
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MC68HC908JK3
Manufacturer Part Number
MC68HC908JK3
Description
MC68HC908JK1
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3.pdf
(210 pages)
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Low Voltage Inhibit (LVI)
16.4 Functional Description
16.5 LVI Control Register (CONFIG2/CONFIG1)
Technical Data
180
Address:
Figure 16-1
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V
determines at which V
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V
Reset:
DD
DD
Read:
Write:
POR:
LVT1
DETECTOR
voltage. The LVI trip voltage selection bits (LVIT1, LVIT0)
drops to below the set trip point.
LOW V
IRQPUD
V
$001E
DD
Bit 7
Figure 16-2. Configuration Register 2 (CONFIG2)
R
0
0
DD
LVT0
shows the structure of the LVI module. The LVI is enabled
Low Voltage Inhibit (LVI)
Figure 16-1. LVI Module Block Diagram
= Reserved
V
V
DD
DD
R
6
0
0
> LVI
< LVI
TRIP
TRIP
DD
= 0
= 1
level the LVI module should take actions.
R
5
0
0
Not affected Not affected
LVIT1
4
0
LVIT0
3
0
LVID
MC68H(R)C908JL3
R
2
0
0
R
1
0
0
MOTOROLA
—
LVI RESET
Rev. 1.0
Bit 0
R
0
0