MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 126

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module (TIM)
10.8 TIM During Break Interrupts
10.9 I/O Signals
Technical Data
126
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state.
(BFCR).)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
Port D shares two of its pins with the TIM. The two TIM channel I/O pins
are PTD4/TCH0 and PTD5/TCH1.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTD4/TCH0 can be configured as
a buffered output compare or buffered PWM pin.
Timer Interface Module (TIM)
(See 7.8.3 Break Flag Control Register
MC68H(R)C908JL3
MOTOROLA
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Rev. 1.0