MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 355

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

27.6.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
IMSG — Ignore Message Bit
CLKS — Clock Bit
R1 and R0 — Rate Select Bits
Freescale Semiconductor
This bit is used to disable the receiver until a new start-of-frame (SOF) is detected.
The nominal BDLC operating frequency (f
bus communications to take place. The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to adjust symbol timing automatically.
These bits determine the amount by which the frequency of the MCU CGMXCLK signal is divided to
form the MUX interface clock (f
They may be written only once after reset, after which they become read-only bits.
The nominal frequency of f
communications to take place. Hence, the value programmed into these bits is dependent on the
chosen MCU system clock frequency per
1 = Disable receiver. When set, all BDLC interrupt requests will be masked and the status bits will
0 = Enable receiver. This bit is cleared automatically by the reception of an SOF symbol or a BREAK
1 = Binary frequency (1.048576 MHz) selected for f
0 = Integer frequency (1 MHz) selected for f
be held in their reset state. If this bit is set while the BDLC is receiving a message, the rest of
the incoming message will be ignored.
symbol. It will then generate interrupt requests and will allow changes of the status register to
occur. However, these interrupts may still be masked by the interrupt enable (IE) bit.
Address:
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
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IMSG
Bit 7
R
1
BARD Offset Bits B0[3:0]
Table 27-2. BDLC Transceiver Delay (Continued)
Figure 27-16. BDLC Control Register 1 (BCR1)
BDLC
= Reserved
CLKS
6
1
BDLC
1000
1001
1010
1011
1100
1101
1110
1111
must always be 1.048576 MHz or 1.0 MHz for J1850 bus
) which defines the basic timing resolution of the MUX interface.
R1
5
1
BDLC
Table 27-3
) must always be 1.048576 MHz or 1 MHz for J1850
BDLC
R0
4
0
Transceiver’s Delays (μs)
Corresponding Expected
BDLC
R
3
0
0
17
18
19
20
21
22
23
24
R
2
0
0
IE
1
0
BDLC CPU Interface
WCM
Bit 0
0
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