MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 339

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

27.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
27.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in
27.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
Freescale Semiconductor
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
MUX INTERFACE
CLOCK
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
D
INPUT
SYNC
Figure 27-5. BDLC Rx Digital Filter Block Diagram
Q
Figure 27-4. BDLC Block Diagram
UP/DOWN
4-BIT UP/DOWN COUTER
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
Figure
OUT
BDLC
27-5.
BDLC
D
LATCH
DATA
parameter in
Q
BDLC MUX Interface
RX DATA OUT
FILTERED
Table
27-3).
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