MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 235

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

20.7 I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB.
PTD4/ATD12/TBCLK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are
PTF4/TBCH0 and PTF5/TBCH1.
20.7.1 TIMB Clock Pin (PTD4/ATD12/TBCLK)
PTD4/ATD12/TBCLK is an external clock input that can be the clock source for the TIMB counter instead
of the prescaled internal bus clock. Select the PTD4/ATD12/TBCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see
width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/ATD12/TBCLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMB clock input. When the PTD4/ATD12/TBCLK pin is the TIMB clock input, it is an input regardless of
the state of the DDRD4 bit in data direction register D.
20.7.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTF4/TBCH0 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins.
20.8 I/O Registers
These I/O registers control and monitor TIMB operation:
20.8.1 TIMB Status and Control Register
The TIMB status and control register:
Freescale Semiconductor
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TIMB status and control register (TBSC)
TIMB control registers (TBCNTH–TBCNTL)
TIMB counter modulo registers (TBMODH–TBMODL)
TIMB channel status and control registers (TBSC0 and TBSC1)
TIMB channel registers (TBCH0H–TBCH0L, TBCH1H–TBCH1L)
Enables TIMB overflow interrupts
Flags TIMB overflows
Stops the TIMB counter
Resets the TIMB counter
Prescales the TIMB counter clock
LMIN
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
or TCLK
HMIN
, is:
20.8.1 TIMB Status and Control
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bus frequency
1
+
t
SU
Register). The minimum TCLK pulse
I/O Signals
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