MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 131

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See
Bandwidth Control
CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock. See
Circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate action, depending on the application.
See
These conditions apply when the PLL is in automatic bandwidth control mode:
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
Freescale Semiconductor
busmax
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10.6
The ACQ bit (See
the filter. See
The ACQ bit is set when the VCO frequency is within a certain tolerance, Δ
the VCO frequency is out of a certain tolerance, Δ
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance, Δ
when the VCO frequency is out of a certain tolerance, Δ
Specifications.
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. See
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, t
Electrical
(PCTL).
Software must wait a given time, t
clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
and require fast startup. The following conditions apply when in manual mode:
Interrupts.
Specifications), after turning on the PLL by setting PLLON in the PLL control register
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Register. If PLL CPU interrupt requests are enabled, the software can wait for a PLL
10.3.2.2 Acquisition and Tracking
10.5.2 PLL Bandwidth Control
10.5.1 PLL Control
al
, after entering tracking mode before selecting the PLL as the
Register.
Modes.
Register.) is a read-only indicator of the mode of
unt
. See
unl
Chapter 28 Electrical
. See
Chapter 28 Electrical
10.3.3 Base Clock Selector
trk
, and is cleared when
acq
Lock
Functional Description
(see
Specifications.
, and is cleared
10.5.2 PLL
Chapter 28
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