MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 259

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

TACH[1:0] — Timer Channel I/O Bits
RxD — SCI Receive Data Input Bit
TxD — SCI Transmit Data Output
22.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
DDRE[7:0] — Data Direction Register E Bits
Freescale Semiconductor
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel
I/O pins or general-purpose I/O pins. (See
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See
18.8.1 SCI Control Register
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. (See
18.8.1 SCI Control Register
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
Address:
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIM. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. (See
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
DDRE7
$000C
Bit 7
0
Figure 22-15. Data Direction Register E (DDRE)
1).
1).
DDRE6
6
0
Table
DDRE5
5
0
22-5).
Table
25.8.4 TIMA Channel Status and Control
NOTE
NOTE
NOTE
DDRE4
22-5).
4
0
DDRE3
3
0
DDRE2
2
0
DDRE1
1
0
DDRE0
Bit 0
Registers).
0
Port E
259