MC68HC908AS60ACFN FREESCALE [Freescale Semiconductor, Inc], MC68HC908AS60ACFN Datasheet - Page 143

• Manufacturer Part Number: MC68HC908AS60ACFN
• Description: M68HC08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See
clock cycles, n
before exiting acquisition mode. A certain number of clock cycles, n
PLL is within the lock mode entry tolerance, Δ
multiple of n
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
clock (see
Influences on Reaction
When defining a limit in software for the maximum lock time, the value must allow for variation due to all
of the factors mentioned in this chapter, especially due to the C
influences.
The calculated lock time is only an indication and it is the customer’s responsibility to allow enough of a
guard band for their application. Prior to finalizing any software and while determining the maximum lock
time, take into account all device to device differences. Typically, applications set the maximum lock time
as an order of magnitude higher than the measured value. This is considered sufficient for all such device
to device variation.
Freescale recommends measuring the lock time of the application system by utilizing dedicated software,
running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock
bit is set. The resultant waveform can be captured on an oscilloscope and used to determine the typical
lock time for the microcontroller and the associated external application circuit.
For example,
Freescale Semiconductor
10.3.3 Base Clock Selector
ACQ
ACQ
The filter capacitor should be fully discharged prior to making any
measurements.
Init. low
/f
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
CGMRDV
, is required to ascertain that the PLL is within the tracking mode entry tolerance, Δ
Time, may slow the lock time considerably.
, and the acquisition to lock time, t
10.3.2.3 Manual and Automatic PLL Bandwidth
t
ACQ
t
LOCK
Circuit), because the factors described in
t
AL
Lock
Lock
NOTE
. Therefore, the acquisition time, t
as calculated above.
t
PLL Configured and switched on
t
AL
TRK
ACQ
Signal on port pin
, is an integer multiple of n
Complete and Lock Set
F
Complete
capacitor and application specific
TRK
Acquisition/Lock Time Specifications
, is required to ascertain that the
Lock
Modes). A certain number of
before selecting the PLL
10.9.2 Parametric
ACQ
, is an integer
TRK
/f
CGMRDV
TRK
143
.
,