MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 86

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

OC1F, OC2F,OC3F, OC4F — Output Compare “x” Flag
4/5F — Input Capture 4/Output Compare 5 Flag
IC1F, IC2F, IC3F — Input Capture “x” Flag
6.4.17 Miscellaneous Timer Interrupt Mask Register 2 (TMSK2)
The bits in TMSK2 correspond bit-for-bit with the bits in the TFLG2 status register. A zero inhibits
the corresponding flag from causing a hardware interrupt. A one enables the corresponding flag to
cause a hardware interrupt.
READ:
WRITE:
RESET:
TO1I — Timer Overflow 1 Interrupt Enable
RTII — RTI Interrupt Enable
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAII — Pulse Accumulator Input Interrupt Enable
MOTOROLA
6-16
RESET:
Set when the 16-bit timer counter register matches the OCx compare register. These bits
are cleared by writing to the TFLG1 register with the corresponding bits (4–7) set.
Set when an input capture occurs on IC4 or an output compare occurs on OC5. This bit
is cleared by writing to the TFLG1 register with bit 3 set.
Set when an input capture occurs on ICx. These bits are cleared by writing to the TFLG1
register with the corresponding bits (0–2) set.
Any time.
Any time.
$00
0 – Interrupt inhibited.
1 – Hardware interrupt requested when TO1F flag set.
0 – Interrupt inhibited.
1 – Hardware interrupt requested when RTIF flag set.
0 – Interrupt inhibited
1 – Hardware interrupt requested when PAOVF flag set
0 – Interrupt inhibited
1 – Hardware interrupt requested when PAIF flag set
$1024
TO1I
7
0
RTII
6
0
PAOVI
5
0
PROGRAMMABLE TIMER
PAII
4
0
TO2I
3
0
5/6I
2
0
6/7I
1
0
0
0
0
TMSK2
MC68HC11G5