MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 132
MC68HC711G5
Manufacturer Part Number
MC68HC711G5
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC711G5.pdf
(195 pages)
- Current page: 132 of 195
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Each unit can generate an interrupt signal (referred to as EVENT1 or EVENT2 in the following
discussion) on a counter match with one of its two compare registers.
The PWM unit is comprised of counter 1 (EVCNT1), two compare registers (ECMP1A and
ECMP1B), an input selector (INPUT1) and an output selector. The PA unit is comprised of Counter
2 (EVCNT2), two compare registers (ECMP2A and ECMP2B) and an input selector (INPUT2).
MOTOROLA
11-2
Mode 0:
Mode 1:
Mode 2:
Mode 4:
*
INPUT1 and INPUT2 can be driven from the E-clock, a second value of the E-clock or from
external signals on the EVI2 and EVI1 input pins. When EVI2 or EVI1 is not being used for
this purpose they may be used as general I/O pins (PH4 and PH5).
Pulse Accumulator modifies PWM output
by adding offset and controlling the clearing
of the PWM
PA and PWM are completely independent
PA Counts the PWM periods (which may
be of variable duration and modulation)
PA acts as programmable 8-bit prescaler
for PWM unit
Figure 11-1. Event Counter Operating Modes
EVENT COUNTER
*
*
*
*
*
*
*
*
INPUT2
INPUT1
INPUT2
INPUT1
INPUT2
INPUT1
INPUT2
INPUT1
PWM
PWM
PWM
PWM
PA
PA
PA
PA
MC68HC11G5
OUTPUT
OUTPUT
OUTPUT
OUTPUT
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