LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 97

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
5.4.5
5.4.6
31-16
15-11
BITS
BITS
31-0
10-6
5-2
1
0
Lower 32 bits of the 64-bit Hash Table
Reserved
PHY Address: For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9118 to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
HASHL—Multicast Hash Table Low Register
This register defines the lower 32-bits of the Multicast Hash Table. Please refer to
"HASHH—Multicast Hash Table High Register"
MII_ACC—MII Access Register
This register is used to control the Management cycles to the PHY.
Offset:
Default Value:
Offset:
Default Value:
5
00000000h
6
00000000h
DATASHEET
DESCRIPTION
DESCRIPTION
97
for further details.
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W
32 bits
Revision 1.1 (05-17-05)
Table 5.4.4,