LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 96

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
5.4.4
BITS
31-0
Upper 32 bits of the 64-bit Hash Table
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in
load this configuration from the EEPROM are also shown.
Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most
HASHH—Multicast Hash Table High Register
The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the
destination address in the incoming frame is used to index the contents of the Hash table. The most
significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit
within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value
of 11111 selects the Bit 31 of the Multicast Hash Table Hi register.
If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All
Multicast” (MCPAS) bit is set (1), then all multicast frames are accepted regardless of the multicast hash
values.
The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast
Hash Table Low register contains the lower 32 bits of the hash table.
Offset:
Default Value:
significant byte and is transmitted/received first.
Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup
31
31
0x78
xx
24
24
23
23
0x56
xx
ADDRH
ADDRL
16
16
4
00000000h
15
15
DATASHEET
0xBC
0x34
8
8
DESCRIPTION
96
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
7
7
0x9A
0x12
0
Attribute:
Size:
0
Figure
5.2. The values required to automatically
0x06
0x05
0x04
0x03
0x02
0x01
0x00
EEPROM
R/W
32 bits
0xBC
0x9A
0xA5
0x78
0x56
0x34
0x12
SMSC LAN9118
Datasheet