LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 113

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.3
SYMBOL
nCS, nRD
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
A[7:5]
A[4:1]
Data Bus
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
PIO Burst Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.2 LAN9118 PIO Burst Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
113
MIN
45
32
13
0
0
0
0
TYP
Revision 1.1 (05-17-05)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns