LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 101

• Manufacturer Part Number: LAN9118_05
• Description: High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
5.4.12
5.5
31-10
BITS
8-7
4-3
9
6
5
2
1
0
(IN DECIMAL)
INDEX
Reserved
Global Unicast Enable (GUE). When set, the MAC wakes up from power-saving mode on receipt of
a global unicast frame. A global unicast frame has the MAC Address [1:0] bit set to 0.
Reserved
Remote Wake-Up Frame Received (WUFR). The MAC, upon receiving a valid Remote Wake-up
frame, sets this bit..
Magic Packet Received (MPR). Tthe MAC, upon receiving a valid Magic Packet, sets this bit.
Reserved
Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is
capable of detecting wake-up frames as programmed in the wake-up frame filter.
Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled.
Reserved
0
1
2
3
WUCSR—Wake-up Control and Status Register
This register contains data pertaining to the MAC’s remote wake-up status and capabilities.
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers.
PHY Register Indexes are shown in
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
PHY Registers
Offset:
Default Value:
the PHY Basic Control Register (Reset) is set.
Table 5.8 LAN9118 PHY Control and Status Register
REGISTER NAME
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
PHY CONTROL AND STATUS REGISTERS
C
00000000h
DATASHEET
Table 5.8, "LAN9118 PHY Control and Status
101
DESCRIPTION
Attribute:
Size:
R/W
32 bits
Revision 1.1 (05-17-05)
Register"below.