LAN9118_05 SMSC [SMSC Corporation], LAN9118_05 Datasheet - Page 102

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LAN9118_05

Manufacturer Part Number
LAN9118_05
Description
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Revision 1.1 (05-17-05)
5.5.1
BITS
15
14
13
12
11
10
9
8
7
(IN DECIMAL)
INDEX
DESCRIPTION
Reset. 1 = software reset. Bit is self-clearing. For best results, when setting
this bit do not set other bits in this register.
Loopback. 1 = loopback mode, 0 = normal operation
Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
enabled (0.12 = 1).
Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
0.13 and 0.8) 0 = disable auto-negotiate process.
Power Down. 1 = General power down-mode, 0 = normal operation.
Note:
Reserved
Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
operation. Bit is self-clearing.
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
is enabled (0.12 = 1).
Collision Test. 1 = enable COL test, 0 = disable COL test
17
18
27
29
30
31
4
5
6
Basic Control Register
Index (In Decimal):
Table 5.8 LAN9118 PHY Control and Status Register (continued)
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
REGISTER NAME
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
PHY CONTROL AND STATUS REGISTERS
0
DATASHEET
102
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
16-bits
RW/SC
RW/SC
TYPE
RW
RW
RW
RW
RW
RW
RO
See
See
SMSC LAN9118
DEFAULT
Note 5.1
Note 5.1
Datasheet
0
0
0
0
0
0
0

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