MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 64

• Manufacturer Part Number: MC68HC705V12CFN
• Description: The Motorola microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

Interrupts
4.7.2 External Interrupt Timing
Advance Information
64
NOTE:
The IRQ flag is cleared automatically during the IRQ vector fetch. The
IRQPC latch is not cleared automatically (to permit interrupt source
differentiation as long as the Interrupt source is present) and must be
cleared from within the IRQ service routine.
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. It is then synchronized internally and serviced as
specified by the contents of $3FFA and $3FFB. The IRQ timing diagram
is shown in
Either a level-sensitive and edge-sensitive trigger or an
edge-sensitive-only trigger is available as a mask option for the IRQ pin
only.
bits are all cleared. The IRQA is useful for cancelling unwanted or
spurious interrupts which may have occurred while servicing the initial
IRQ interrupt.
IRQ1 (PORT)
IRQn (PORT)
(MCU)
IRQ
IRQ
.
.
.
Figure 4-4. External Interrupts Timing Diagram
Figure
4-4.
Interrupts
t
ILIH
t
ILIH
t
ILIL
MC68HC705V12
MOTOROLA
—
Rev. 3.0