MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 136
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MC68HC705V12CFN
Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705V12CFN.pdf
(248 pages)
- Current page: 136 of 248
- Download datasheet (2Mb)
Analog-to-Digital (A/D) Converter
13.7 A/D during Wait Mode
13.8 A/D during Stop Mode
Advance Information
136
NOTE:
NOTE:
The A/D converter continues normal operation during wait mode. To
decrease power consumption during wait mode, it is recommended that
both the ADON and ADRC bits in the A/D status and control registers be
cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz, it is recommended that
the ADRC bit be cleared.
As the A/D converter continues to function normally in wait mode, the
COCO bit is not cleared.
In stop mode, the comparator and charge pump are turned off and the
A/D ceases to function. Any pending conversion is aborted. When the
clocks begin oscillation upon leaving stop mode, a finite amount of time
passes before the A/D circuits stabilize enough to provide conversions
to the specified accuracy. Normally, the delays built into the device when
coming out of stop mode are sufficient for this purpose so that no explicit
delays need to be built into the software.
Although the comparator and charge pump are disabled in stop mode,
the A/D data and status/control registers are not modified. Disabling the
A/D prior to entering stop mode will not affect the stop mode current
consumption.
Analog-to-Digital (A/D) Converter
MC68HC705V12
MOTOROLA
—
Rev. 3.0
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