MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 118
MC68HC705V12CFN
Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705V12CFN.pdf
(248 pages)
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Pulse Width Modulators (PWMs)
11.4.2 PWMB Control Register
Advance Information
118
NOTE:
Address:
PSA1B, PSA0B, and PSB3B PSB0B — PWM Clock Rate Bits
Any non-zero value of PSA1B PSA0B forces PB5 to the PWMB output
state. If PSA1B PSA0B = 00, PB5 is determined by the port B data and
data direction registers as described in
Input/Output
Reset:
Read:
Write:
These bits select the input clock rate for PWMB and determine the
period as shown in
as the corresponding bits in the PWMA control register except they
affect the PWMB output pin.
PSA1B–
PSA0B
00
01
10
11
PSA1B
$0039
Bit 7
Figure 11-6. PWMB Control Register (PWMBC)
0
Pulse Width Modulators (PWMs)
(I/O).
= Unimplemented
0000–1111
0000–1111
0000–1111
PSA0B
PSB3B–
PSB0B
xxxx
6
0
Table 11-2. PWMB Clock Rates
Table
5
0
0
RCLKB
11-2. These bits function exactly the same
f
f
f
OP
OP
OP
Off
/16
/1
/8
4
0
0
f
f
OP
f
OP
OP
/16 – f
Section 7. Parallel
/8 – f
SCLKB
PSB3B
/1 – f
Off
3
0
OP
OP
OP
/128
/16
/256
MC68HC705V12
PSB2B
2
0
f
OP
f
f
OP
OP
/1024 – f
PWMB OUT
/512 – f
/64 – f
PSB1B
1
0
Off
MOTOROLA
OP
—
OP
OP
/1024
/8192
/16384
Rev. 3.0
PSB0B
Bit 0
0
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