MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 179

• Manufacturer Part Number: MC68HC705V12CFN
• Description: The Motorola microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

14.7.4 BDLC State Vector Register
MC68HC705V12
MOTOROLA
—
Rev. 3.0
Address:
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
I0, I1, I2, and I3 — Interrupt Source Bits
Reset:
BSVR
Read:
Write:
$0C
$1C
$00
$04
$08
$10
$14
$18
$20
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits is listed in
Byte Data Link Controller – Digital (BDLC–D)
$003C
Figure 14-20. BDLC State Vector Register (BSVR)
Bit 7
I3
0
0
0
0
0
0
0
0
1
0
0
I2
0
0
0
0
1
1
1
1
0
= Unimplemented
Table 14-5. BDLC Interrupt Sources
I1
0
0
1
1
0
0
1
1
0
6
0
0
I0
0
1
0
1
0
1
0
1
0
Cyclical redundancy check (CRC) error
I3
BDLC Tx data register empty (TDRE)
5
0
BDLC Rx data register full (RDRF)
Symbol invalid or out of range
Received IFR byte (RXIFR)
No interrupts pending
Byte Data Link Controller – Digital (BDLC–D)
I2
Loss of arbitration
4
0
Interrupt Source
Received EOF
Wakeup
I1
3
0
Table
I0
2
0
BDLC CPU Interface
Advance Information
14-5.
1
0
0
8 (Highest)
0 (Lowest)
Priority
1
2
3
4
5
6
7
Bit 0
0
0
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