PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 410

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2XK20/4XK20
Extended Instruction Set
F
Fail-Safe Clock Monitor .............................................. 38, 283
Fast Register Stack ............................................................ 66
Firmware Instructions ....................................................... 299
Flash Program Memory ...................................................... 85
G
General Call Address Support ......................................... 207
GOTO ............................................................................... 320
H
Hardware Multiplier ............................................................ 99
High/Low-Voltage Detect ................................................. 277
DS41303B-page 408
Interrupts
Synchronous Master Mode .............................. 243, 247
Synchronous Slave Mode
ADDFSR .................................................................. 342
ADDULNK ................................................................ 342
and Using MPLAB Tools .......................................... 348
CALLW ..................................................................... 343
Considerations for Use ............................................ 346
MOVSF .................................................................... 343
MOVSS .................................................................... 344
PUSHL ..................................................................... 344
SUBFSR .................................................................. 345
SUBULNK ................................................................ 345
Syntax ...................................................................... 341
Fail-Safe Condition Clearing ...................................... 38
Fail-Safe Detection .................................................... 38
Fail-Safe Operation .................................................... 38
Reset or Wake-up from Sleep .................................... 38
Associated Registers ................................................. 93
Control Registers ....................................................... 86
Erase Sequence ........................................................ 90
Erasing ....................................................................... 90
Operation During Code-Protect ................................. 93
Reading ...................................................................... 89
Table Pointer
Table Pointer Boundaries .......................................... 88
Table Reads and Table Writes .................................. 85
Write Sequence ......................................................... 91
Writing To ................................................................... 91
Introduction ................................................................ 99
Operation ................................................................... 99
Performance Comparison .......................................... 99
Applications .............................................................. 281
Associated Registers ............................................... 281
Synchronous Mode .......................................... 243
Asychronous Receive ...................................... 229
Asychronous Transmit ..................................... 225
Associated Registers, Receive ........................ 246
Associated Registers, Transmit ............... 244, 247
Reception ......................................................... 245
Transmission .................................................... 243
Associated Registers, Receive ........................ 248
Reception ......................................................... 248
Transmission .................................................... 247
EECON1 and EECON2 ..................................... 86
TABLAT (Table Latch) Register ......................... 88
TBLPTR (Table Pointer) Register ...................... 88
Boundaries Based on Operation ........................ 88
Protection Against Spurious Writes ................... 93
Unexpected Termination .................................... 93
Write Verify ........................................................ 93
Advance Information
HLVD. See High/Low-Voltage Detect. ............................. 277
HLVDCON Register ......................................................... 277
I
I/O Ports ........................................................................... 115
I
ID Locations ............................................................. 283, 297
INCF ................................................................................ 320
INCFSZ ............................................................................ 321
In-Circuit Debugger .......................................................... 297
In-Circuit Serial Programming (ICSP) ...................... 283, 297
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 346
Indirect Addressing ............................................................ 81
INFSNZ ............................................................................ 321
Initialization Conditions for all Registers ...................... 57–60
Instruction Cycle ................................................................ 67
Instruction Flow/Pipelining ................................................. 67
Instruction Set .................................................................. 299
2
C Mode (MSSP)
Characteristics ......................................................... 366
Current Consumption ............................................... 279
Effects of a Reset .................................................... 281
Operation ................................................................. 278
Setup ....................................................................... 279
Start-up Time ........................................................... 279
Typical Application ................................................... 281
Acknowledge Sequence Timing .............................. 217
Baud Rate Generator .............................................. 210
Bus Collision
Clock Arbitration ...................................................... 211
Clock Stretching ....................................................... 203
Clock Synchronization and the CKP bit (SEN = 1) .. 204
Effects of a Reset .................................................... 218
General Call Address Support ................................. 207
I
Master Mode ............................................................ 208
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 218
Operation ................................................................. 196
Read/Write Bit Information (R/W Bit) ............... 196, 197
Registers ................................................................. 192
Serial Clock (RC3/SCK/SCL) ................................... 197
Slave Mode .............................................................. 196
Sleep Operation ....................................................... 218
Stop Condition Timing ............................................. 217
and Standard PIC18 Instructions ............................. 346
Clocking Scheme ....................................................... 67
ADDLW .................................................................... 305
ADDWF .................................................................... 305
ADDWF (Indexed Literal Offset Mode) .................... 347
2
C Clock Rate w/BRG ............................................. 210
During Sleep .................................................... 281
During a Repeated Start Condition .................. 221
During a Stop Condition .................................. 222
10-Bit Slave Receive Mode (SEN = 1) ............ 203
10-Bit Slave Transmit Mode ............................ 203
7-Bit Slave Receive Mode (SEN = 1) .............. 203
7-Bit Slave Transmit Mode .............................. 203
Operation ......................................................... 209
Reception ........................................................ 214
Repeated Start Condition Timing .................... 213
Start Condition Timing ..................................... 212
Transmission ................................................... 214
and Arbitration ................................................. 218
Addressing ....................................................... 196
Reception ........................................................ 197
Transmission ................................................... 197
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