PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 141

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 11-2:
11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 11-1:
© 2007 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: Shaded cells are not used by Timer0.
Note 1:
Note:
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
Name
Prescaler
register
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
T0SE
T0CS
T0PS<2:0>
PSA
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register, Low Byte
Timer0 Register, High Byte
GIE/GIEH PEIE/GIEL TMR0IE
F
TMR0ON
OSC
RA7
Bit 7
REGISTERS ASSOCIATED WITH TIMER0
/4
which
(1)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
determine
T08BIT
RA6
Bit 6
(1)
Programmable
Prescaler
3
the
T0CS
Bit 5
RA5
Advance Information
prescaler
0
1
INT0IE
T0SE
Bit 4
RA4
(2 T
Sync with
Internal
Clocks
CY
Delay)
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
PIC18F2XK20/4XK20
RBIE
Bit 3
PSA
RA3
Timer0 Interrupt
TMR0IF
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
RA2
TMR0L
8
8
INT0IF
T0PS1
Bit 1
RA1
High Byte
TMR0H
TMR0
8
8
8
T0PS0
RBIF
Bit 0
RA0
DS41303B-page 139
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L
Internal Data Bus
on page
Values
Reset
58
58
57
58
60