PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 116
PIC18F23K20-E/MLQTP
Manufacturer Part Number
PIC18F23K20-E/MLQTP
Description
28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F23K20-EMLQTP.pdf
(420 pages)
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PIC18F2XK20/4XK20
9.8
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
REGISTER 9-10:
DS41303B-page 114
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset.
R/W-0
IPEN
RCON Register
See Register 4-1 for additional information.
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (Mid-Range Compatibility mode)
SBOREN: Software BOR Enable bit
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
SBOREN
R/W-1
RCON: RESET CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
U-0
—
Advance Information
R/W-1
RI
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
TO
R-1
PD
© 2007 Microchip Technology Inc.
x = Bit is unknown
POR
R/W-0
(1)
R/W-0
BOR
bit 0
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