MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 53

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

The maximum transfer rate is calculated from the fact that 16 bits are moved every 8 clocks.
The calculation is as follows:
The IDMA controller block diagram is shown in Figure 3-1.
3.1.2 IDMA Registers (Independent DMA Controller)
The IDMA has six registers that define its specific operation. These registers include a 32-
bit source address pointer register (SAPR), a 32-bit destination address pointer register
MOTOROLA
(2 bus cycles) x (4 clocks/bus cycle)
16 bits x 16M clocks/sec
31
31
31
IBCLR
IDBG
IDBR
Figure 3-1. IDMA Controller Block Diagram
DESTINATION ADDRESS POINTER REGISTER
MC68302 USER’S MANUAL
SOURCE ADDRESS POINTER REGISTER
SDMA ADDRESS AND FC REGISTER
15
15
15
CONTROL
=
LOGIC
IDMA
CHANNEL MODE REGISTER
2 bytes x 16M clocks/sec
BYTE COUNT REGISTER
SDMA DATA REGISTER
8 clocks
7
7
CHANNEL STATUS REGISTER
FUNCTION CODE REGISTER
System Integration Block (SIB)
DONE
DACK
DREQ
INTERRUPT REQUEST
=
0
0
0
0
0
0
0
0
4M bytes
sec
3-3