MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 108

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

System Integration Block (SIB)
The IMP bus arbiter also supports an M68000 core low-interrupt latency option. When the
M68000 core processor has an unmasked interrupt request, it asserts an internal interrupt
pending signal (IPEND). The bus arbiter uses this signal according to BCLM in the SCR to
assert external (BCLR) and internal bus-clear (IBCLR) signals. These bus-clear signals al-
low the M68000 core to eliminate long latencies potentially associated with an external bus
master or the IDMA, respectively.
The external BCLR is asserted whenever 1) one of the SDMA channels requests the bus
when the IDMA is not the bus master or 2) the M68000 core has an unmasked pending in-
terrupt request, provided BCLM in the SCR is set. In this case, BCLR will be asserted until
the interrupt priority active (IPA) bit in the SCR is cleared. To implement this feature, BCLR
would be used to force external devices to release bus ownership.
IBCLR to the IDMA is asserted whenever 1) an external bus master requests the bus (BR
asserted); 2) the M68000 core has an unmasked pending interrupt request, provided BCLM
in the SCR is set and the IDMA request is internally generated, and in this case, BCLR will
be asserted until IPA is cleared (Note that BCLR could be used to negate DREQ when the
IDMA is in external request mode); 3) the M68000 CPU is disabled, and BCLR is asserted.
The IBCLR signal causes the IDMA to release bus ownership at the end of the current op-
erand transfer. IBCLR is not routed to the SDMA channels since they always release bus
ownership after one operand transfer.
RMC is issued by the M68000 core and can be used by the internal bus arbiter to delay is-
suance of BG during read-modify-write cycles. This is controlled by the RMCST bit in the
SCR. Otherwise, the MC68000/MC68008 core may be forced off the bus after any bus cy-
cle.
3.8.5.2 External Bus Arbitration
An external bus master may gain ownership of the M68000 bus by asserting the bus request
(BR) pin. After gaining ownership, it may access the IMP registers or RAM or any system
memory address. Chip selects and system control functions, such as the hardware watch-
dog, continue to operate.
3-58
BR Pin
SDMA
IDMA
M68000 Interrupts
M68000
NOTES:
1. The SDMA on a given IMP always has a higher priority than the IDMA on that IMP.
2. This table assumes the M68000 core is not in disable CPU mode. In disable CPU mode, the SDMA
3. “BCLR Used” means that the BCLR pin is used externally to force the external bus master off the bus,
4. The bus arbitration priority for IDMA in the two rightmost columns of the table applies only to the case
and IDMA make requests to the M68000 bus when they wish to become bus masters.
even though its priority is still the highest in the system from the standpoint of the IMP bus arbiter.
when the IDMA request is internally generated; for the cases of external request, the bus arbitration
priority of IDMA is right below that of SDMA.
BCLR Ignored
BCLM = 0
Table 3-10. Bus Arbitration Priority Table
SDMA
IDMA
BR Pin
M68000 Interrupts
M68000
BCLR Used
BCLM = 0
MC68302 USER’S MANUAL
BR Pin
SDMA
M68000 Interrupts
IDMA
M68000
BCLR Ignored
4
BCLM = 1
SDMA
M68000 Interrupts
IDMA
BR Pin
M68000
BCLR Used
4
BCLM = 1
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