MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 143

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
three channels of a PCM highway. Each protocol-type implementation uses identical buffer
structures to simplify programming.
The following protocols are supported: HDLC/SDLC, BISYNC, synchronous and asynchro-
nous DDCMP, UART, several transparent modes, and V.110 rate adaption support. Each
protocol can be implemented with IDL, GCI, PCM, or NMSI physical layer interfaces (see
4.4 Serial Channels Physical Interface) and can be configured to operate in either echo or
loopback mode. Echo mode provides a return signal from an SCC by retransmitting the re-
ceived signal. Loopback mode is a local feedback connection allowing an SCC to receive
the signal it is transmitting. (Echo and loopback mode for multiplexed interfaces are dis-
cussed in 4.4 Serial Channels Physical Interface).
The receive and transmit section of each SCC is supported with one of the six dedicated
SDMA channels (see 4.2 SDMA Channels). These channels transfer data between the
SCCs and either external RAM or on-chip dual-port RAM. This function is transparent to the
user, being enabled and controlled according to the configuration of each SCC channel.
Each SCC can be clocked by either an external source (with the clock pins RCLK or TCLK)
or by an internal source through a baud rate generator for each SCC channel. The baud rate
generator can derive its clock from the main IMP clock or from a separate input clock. The
SCC transmitter and receiver sections are independent and may be clocked at different
rates.
The SCCs exhibit two types of performance limitations. The first type is a hardware clocking
limit, which is the same for each SCC. The SCC clocks must not exceed a ratio of 1:2.5 serial
clock (RCLK or TCLK) to parallel clock (EXTAL). Thus, for a 16.67-MHz system clock fre-
quency, the serial clock must not exceed 6.67 MHz. The second type concerns the system
data rate. The SDMA channels and CP main controller must have enough time to service
the SCCs, thus preventing FIFO underruns and overruns in the SCCs. This requirement de-
pends on a number of factors discussed in more detail in Appendix A SCC Performance.
Each SCC supports the standard seven-line modem interface (also referred to as NMSI)
with the signals RXD, TXD, RCLK, TCLK, RTS, CTS, and CD. Other modem signals (such
as DSR and DTR) may be supported through the parallel I/O pins. A block diagram of the
SCC is depicted in Figure 4-11.
To provide extra modem serial output lines, the user must define I/O port A or B pins as out-
puts in the port A/B data direction register and write to the port A/B data register to cause
the state of the pin to change. Extra serial input lines with interrupts may be supported by
defining the port B pins as inputs in the port B data direction register. When a change in the
state of the pin occurs, the interrupt handler may assert or negate the extra outputs to sup-
port the hand-shaking protocol. (See 3.3 Parallel I/O Ports for related details.)
MOTOROLA
MC68302 USER’S MANUAL
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