MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 49

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

#
## The output latches are undefined at total system reset.
2.9 EVENT REGISTERS
The IMP contains a few special registers designed to report events to the user. They are the
channel status register (CSR) in the independent DMA, the interrupt pending register (IPR)
and interrupt in-service register (ISR) in the interrupt controller, the timer event register 1
(TER1) in timer 1, the TER2 in timer 2, serial communication controller event register 1
(SCCE1) in SCC1, SCCE2 in SCC2, and SCCE3 in SCC3. Events in these register are al-
ways reported by a bit being set.
During the normal course of operation, the user software will clear these events after recog-
nizing them. To clear a bit in one of these registers, the user software must WRITE A ONE
TO THAT BIT. Writing a zero has no effect on the register. Thus, in normal operation, the
hardware only sets bits in these registers; whereas, the software only clears them.
This technique prevents software from inadvertently losing the indication from an event bit
that is “set” by the hardware between the software read and the software write of this regis-
ter.
All these registers are cleared after a total system reset (RESET and HALT asserted togeth-
er) and after the M68000 RESET instruction. Also some of the blocks (IDMA, timer1, timer2,
and communication processor) have a reset (RST) bit located in a register in that block. This
RST bit will reset that entire block, including any event registers contained therein.
Examples:
MOTOROLA
!
! Base + 8A8
1. To clear bit 0 of SCCE1, execute "MOVE.B #$01,SCCE1"
Base + 8A0
Base + 8A2
Base + 8A4
Base + 8A6
Base + 8A9
Base + 8AA
Base + 8AB
Base + 8AC
Base + 8AD
Base + 8AE
Base + 8B0
Base + 8B2 #
Base + 8B4 #
Base + 8B6
Base + FFF
Reset only upon a total system reset (RESET and HALT assert together), but not on the execution of an M68000
RESET instruction. See the RESET pin description for details.
Event register with special properties (see 2.9 Event Registers).
•
•
•
SPMODE
SIMODE
SCCM3
SIMASK
SCON3
SCCE3
SCCS3
SCM3
DSR3
RES
RES
RES
RES
RES
16
16
16
16
16
16
16
16
8
8
8
8
8
8
Table 2-9. Internal Registers
MC68302 USER’S MANUAL
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCC3
SCM
SI
SI
Reserved
SCC3 Configuration Register
SCC3 Mode Register
SCC3 Data Sync. Register
SCC3 Event Register
Reserved
SCC3 Mask Register
Reserved
SCC3 Status Register
Reserved
Reserved
SCP, SMC Mode and Clock
Serial Interface Mask Register
Serial Interface Mode Register
Reserved
(Not Implemented)
Control Register
MC68000/MC68008 Core
7E7E
0004
0000
0000
FFFF
0000
00
00
00
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