MC68000 MOTOROLA [Motorola, Inc], MC68000 Datasheet - Page 124

• Manufacturer Part Number: MC68000
• Manufacturer: MOTOROLA [Motorola, Inc]

Communications Processor (CP)
The SDMA channels implement bus-cycle-stealing data transfers controlled by microcode
in the CP main controller. Having no user-accessible registers associated with them, the
channels are effectively controlled by the choice of SCC configuration options.
When one SDMA channel needs to transfer data to or from external memory, it will request
the M68000 bus with the internal signal SDBR, wait for SDBG, and then only assert the ex-
ternal signal BGACK (see 3.8.5 Bus Arbitration Logic). It remains the bus master for only
one bus cycle. The six SDMA channels have priority over the IDMA controller. If the IDMA
is bus master when an SDMA channel needs to transfer over the M68000 bus, the SDMA
will steal a cycle from the IDMA with no arbitration overhead while BGACK remains contin-
uously low and BCLR remains high. Each SDMA channel may be programmed with a sep-
arate function code, if desired. The SDMA channel will read 16 bits at a time. It will write 8
bits at a time except during the HDLC or transparent protocols where it writes 16 bits at a
time. Each bus cycle is a standard M68000-type bus cycle. The chip select and wait state
generation logic on the MC68302 may be used with the SDMA channels.
4-4
COMMUNICATIONS
MICROCODED
CONTROLLER
M68000
(RISC)
CORE
When external buffer memory is used, the M68000 bus arbitra-
tion delay must be less than what would cause the SCC internal
FIFOs to overrun or underrun. This aspect is discussed in more
detail in 4.5 Serial Communication Controllers (SCCs) and in
Appendix A SCC Performance.
Figure 4-2. Three Serial Data Flow Paths
CONTROLLER
INTERRUPT
MC68302 USER’S MANUAL
CHANNELS
CHANNELS
1
3 SERIAL
6 DMA
PERIPHERAL BUS
NOTE
1 GENERAL-
PURPOSE
CHANNEL
DMA
2
SYSTEM BUS
1152 BYTES
DUAL-PORT
CHANNELS
OTHER
SERIAL
68000
RAM
3
ADDITIONAL
FEATURES
3 TIMERS
AND
MC68302 IMP
PERIPHERALS
RAM / ROM
OTHER
MOTOROLA