ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 47

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

3.5.3.9
Figure 3-18. Timer 0 Pulse Width Modulation
3.5.3.10
4711B–4BMCU–01/05
Timer
State
Overflow
Interrupt
T0OUT1
(BP41)
Timer
Clock
Timer 0 Pulse Width Modulation Mode
Pulse Density Modulation Mode
t_hi = (comparator value)
t_low = (255-comparator value)
A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark
space ratio. It is often used as a simple method for D/A conversion, where the high period is pro-
portional to the digital value to be converted. Therefore by connecting a simple low-pass RC
network to the PWM signal, the analog value can be retrieved.
Timer 0 generates the PWM signal by comparing the state of the free running up counter with
the contents of the compare register (see
ister value, then the BP41 output is high. If the result is greater or equal to the compare register
value, then the BP41 output is set low. Thus, the high phase of the PWM signal is directly pro-
portional to the compare register contents. A total of 256 possible discrete mark space ratios can
be generated ranging from a continuous low signal over a variable pulse width signal to a contin-
uous high signal. The PWM signal has a repetition period of 256 clocks, an interrupt (if
unmasked) being generated on every overflow event. Care should be taken if the SYSCL clock
is used as the PWM clock source because it may stop if the CPU goes into SLEEP mode (see
section “Power-Down Modes”).
Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal
where the high and low signal phases are always continuous during a single repetition cycle, the
PDM distributes these evenly as a series of pulses (see
advantage that, if used together with an RC smoothing filter for D/A conversion, either the ripple
is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller
or the clock frequency lower. To generate the PDM output on BP41, the pulse density is con-
trolled by the contents of the compare register in the same way as the PWM generation. Each of
the pulses has a width equal to the counter clock period.
255
0
t_hi
1
2
clock period
3
4
clock period
Timer = compare register (= 4)
t_low
255
Figure
0
1
3-18). If the result is less than the compare reg-
3
4
Figure 3-19 on page
255
0
1
ATAM510
48). This has the
3
4
47