ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 10

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

2.5
2.5.1
2.5.2
10
Interrupt Structure
ATAM510
Interrupt Processing
Interrupt Latency
The MARC4 can handle interrupts with eight different priority levels. They can be generated
from the internal and external interrupt sources or by a software interrupt from the CPU itself.
Each interrupt level has a hard-wired priority and an associated vector for the service routine in
the ROM (see
rupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be
registered, but the interrupt routine only started after the I flag is set. All interrupts can be
masked, and the priority individually software configured by programming the appropriate control
register of the interrupting module (see section “Peripheral Modules”).
For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-
bit wide interrupt pending and interrupt active registers. The interrupt controller samples all inter-
rupt requests during every non-I/O instruction cycle and latches these in the interrupt pending
register. Whenever an interrupt request is detected, the CPU interrupts the program currently
being executed, on condition that no higher priority interrupt is present in the interrupt active reg-
ister. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle.
During this cycle a short call (SCALL) instruction to the service routine is executed and the cur-
rent PC is saved on the return stack.
An interrupt service routine is completed with the RTI instruction. This instruction resets the cor-
responding bits in the interrupt pending/active register and fetches the return address from the
return stack to the program counter. When the interrupt-enable flag is reset (triggering of inter-
rupt routines are disabled), the execution of new interrupt service routines is inhibited but not the
logging of the interrupt requests in the interrupt pending register. The execution of the interrupt
is delayed until the interrupt-enable flag is set again. Note that interrupts are only lost if an inter-
rupt request occurs while the corresponding bit in the pending register is still set (i.e., the
interrupt service routine is not yet finished).
After a master reset (power-on, brown-out or watchdog reset), the interrupt-enable flag and the
interrupt pending and interrupt active registers are all reset.
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-
tine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles
depending on the state of the core).
Table 2-1 on page
11). The programmer can postpone the processing of inter-
4711B–4BMCU–01/05