ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 27

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

3.2.5
Figure 3-4.
3.2.5.1
4711B–4BMCU–01/05
BPx3
BPx2
BPx1
BPx0
Bi-directional Port A and Port B with Port Monitor Function
Connected to Ports A and B (x = A or B)
Port Monitor Interrupt Priority Register (PxIPR)
Port Monitor Module of Port A and Port B
In addition to the standard I/O functions described in section “Bi-directional Port 5, Port 7 and
Port C”, both Port A (BPA3 - BPA0) and Port B (BPB3 - BPB0) are equipped with Schmitt trigger
inputs and a port monitor module. This module is connected across all four port pins (see
3-4) and is intended for monitoring those pins selected by control bits Enx3 - Enx0 and generat-
ing an interrupt when the first pin leaves a preselected logical default idle state. This state is
defined by control bit ITRx. Transitions on other pins will only cause an interrupt if the other pins
have first returned to the idle state. This, for example is useful for interrupt initiated port scanning
without the power consuming task of continuously polling for port activity.
Using the Port Interrupt Control Register (PxICR), pins can be individually selected. A non-
selected pin cannot generate an interrupt. The Port Interrupt Priority Register (PxIPR) allows
masking of each interrupt, definition of the interrupt edge and programming of the interrupt prior-
ity levels. When programming or reprogramming either of the port monitor control registers, any
previously generated interrupt on that port which has not yet been acknowledged by the CPU or
an interrupt generated by the reprogramming itself is automatically cleared. Port A can also be
used for a mask programmable coded reset. For more information see section “Hardware
Reset”.
The Port Interrupt Priority Registers PAIPR and PBIPR are I/O mapped to the primary address
registers of the Port Monitor Module addresses '2'h and '3'h respectively. The Port Interrupt Con-
trol Registers PAICR and PBICR are mapped to the corresponding auxiliary registers.
x = 'A' (Port A) or 'B' (Port B)
IMx
ITRx
PRx2..1
PxICR
PxIPR
ENx3
ENx2
Interrupt Mask
Interrupt Transition
Interrupt Priority code
Bit 3
IMx
ENx1
ENx0
ITRx
Bit 2
IMAx
PRx2
Bit 1
ITRx
PRx1
Bit 0
PRx1
(Port A) Primary register address: '2'hex
(Port B) Primary register address: '3'hex
PRx2
Decoder
2:4
PxIPR
Reset value: 1111b
PRx1 PRx2
0
0
1
1
INT7
INT5
INT3
INT1
ATAM510
1
0
1
0
INT7
INT5
INT3
INT1
Figure
27