ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 44

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

3.5.3.4
3.5.3.5
3.5.3.6
44
ATAM510
Timer 0 Compare Register (T0CP) - Byte Write
Timer 0 Capture Register (T0CA) - Byte Read
Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle)
T0CP3 ... T0CP0 - Timer 0 Compare Register Data (low nibble) - first write cycle
T0CP7 ... T0CP4 - Timer 0 Compare Register Data (high nibble) - second write cycle
The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see sec-
tion “Addressing Peripherals”). First, the low nibble data is written and is then followed by the
high nibble. Any timer interrupts are automatically suppressed until the complete compare value
has been transferred.
T0CA7. .. T0CA4 - Timer 0 Capture Register Data (high nibble) - first read cycle
T0CA3 ... T0CA0 - Timer 0 Capture Register Data (low nibble) - second read cycle
Note:
The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike writing to
the compare register, the high nibble is read first followed by the low nibble. The 8-bit timer state
is captured on reading the first nibble and held until the complete byte has been read. During
this transfer, the timer is free to continue counting.
In the free running counter mode, Timer 0 can be used as an event counter for summing exter-
nal event pulses on BP40, or as a timer with an internal time-based clock. When enabled, the
counter will count up generating an output signal on BP41 whenever the counter contents match
the compare register (see
pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode.
Interrupts (if not masked) are generated every 256 clocks on the overflow condition. The current
counter state can be read at any time by reading the capture register,. The compare register has
no effect on the counter cycle time and will not influence interrupts.
T0CP
T0CA
If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 = MSB,
T0CA1 = MSB - 1 .... T0CA6 = LSB + 1, T0CA7 = LSB.
First write
cycle
Second write
cycle
First write
cycle
Second write
cycle
Figure 3-14 on page
Subport address (indirect read access): '9'hex of Port address '9'hex
Bit 3
T0CP3
Bit 7
T0CP7
Subport address (indirect read access): '9'hex of Port address '9'hex
Bit 7
T0CA7
Bit 3
T0CA3
Bit 2
T0CP2
Bit 6
T0CP6
Bit 6
T0CA6
Bit 2
T0CA2
Bit 1
T0CP1
Bit 5
T0CP5
Bit 5
T0CA5
Bit 1
T0CA1
45). This signal can appear either as a strobe
Bit 0
T0CP0
Bit 4
T0CP4
Bit 4
T0CA4
Bit 0
T0CA0
Reset value: xxxxb
Reset value: xxxxb
Reset value: xxxxb
Reset value: xxxxb
4711B–4BMCU–01/05