ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 35

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

3.4
3.5
4711B–4BMCU–01/05
Watchdog Timer
Timer/Counter Module (TCM)
The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the
select code (FS2-FS0). This allows independent programming of interval times for INTA and
INTB.
Figure 3-10. Watchdog Timer
The watchdog timer is a 17-stage binary divider clocked by SUBCL generated within the clock
module (see
configurable option whereby it must be periodically reset from the application program. The pro-
gram cannot disable the watchdog. If the CPU finds itself for an extended length of time in
SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will
overflow, thus forcing the NRST pin low. This initiates a master reset. The timeout period can be
set to 0.5, 1 or 2 seconds (if SUBCL = 32 kHz) by using a configurable option.
To reset the watchdog, the program must perform an IN-instruction on the address CWD
('3'hex). No relevant data is usually received. The operation is therefore normally followed by a
DROP to flush the data from the stack.
The TCM consists of two timer/counter blocks (Timer 0 and Timer 1) which can be used sepa-
rately, or together as a single 16-bit counter/timer (see
on page
can be selected and divided under program control using the Timer/Counter Control Register
(TCCR), the Timer 0 Control Register (T0CR) and the Timer 1 Control Register (T1CR). Capture
and compare registers (T0CA,T1CA,T0CP and T1CP) not only allow event counting, but also
the generation of various timed output waveforms including programmable frequencies, modu-
lated melody tones, Pulse Width Modulated (PWM) and Pulse Density Modulated (PDM) output
signals. When in one of these signal generation modes, the capture register acts as timer
shadow register, the current timer state is frozen whenever read by the CPU. Timer 0 is further
equipped to perform a variety of time measurement operations. In this mode the capture register
is used together with the gating logic for performing asynchronous, externally triggered snapshot
measurements. These measurements include single input pulse width and period measure-
ments and also dual input phase and positional measurements. The mode configuration is set in
the Timer 0 and Timer 1 Mode Registers (T0MO and T1MO).
40). Each timer can be supplied by various internal or external clock sources. These
WDRES
SUBCL
Master
Figure 2-9 on page 16
NRST
Reset
Read
CK
R
R
R
and
R
17-stage binary counter
R
Figure 3-10 on page
V
R
*
DD
Watchdog enable
R
R
R
Figure 3-11 on page 36
R
R
2
14
R
35). It can only be enabled as a
*
R
R
2
*
15
Configurable option
*
R
R
ATAM510
R
2
and
16
*
Figure 3-13
35