ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 22
ATAM510X-ILQY
Manufacturer Part Number
ATAM510X-ILQY
Description
MARC4 4-bit MTP Universal Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM510X-ILQY.pdf
(72 pages)
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Figure 3-1.
22
ATAM510
Example of
qFORTH
Program
Code
Module ASW
Auxiliary Switch
Example of I/O Addressing
Primary Reg.
Module
1
2
3
1
2
3
1
2
3
3
1
2
3
3
1
2
(Address Pointer)
2
Aux. Reg.
SPort_Data (lo) Addr. (M1) OUT
SPort_Data (hi) Addr. (M1) OUT
(Subport Register Read Byte)
Addr. (SPort) Addr. (M1) OUT
(Subport Register Write)
Addr. (M1) Addr. (ASW) OUT
Addr. (SPort) Addr. (M1) OUT
SPort_Data Addr. (M1) OUT
(Subport Register Read)
Addr. (M1) Addr. (ASW) OUT
Addr. (SPort) Addr. (M1) OUT
(Subport Register Write Byte)
Addr. (M1) Addr. (ASW) OUT
Addr. (SPort) Addr. (M1) OUT
Addr. (M1) Addr. (ASW) OUT
Addr. (M1) Addr. (ASW) OUT
(Auxiliary Register Read)
Indirect Subport Access
1
Module M1
Addr. (M1) IN
Addr. (M1) IN
Addr. (M1) IN
Addr. (M1) IN
Bank of
Primary Reg.
Subport Eh
Subport Fh
Subport 0
Subport 1
3
I/O bus
6
6
6
4
5
6
4
5
5
Addr. (ASW) = Auxiliary Switch Module Address
Addr. (Mx) = Module Mx Address
Addr. (SPort) = Subport Address
Prim._Data = data to be written into Primary Register
Aux._Data = data to be written into Auxiliary Register
Aux._Data (lo) = data to be written into Auxiliary Register (low nibble)
Aux._Data (hi) = data to be written into Auxiliary Register (high nibble)
SPort_Data (lo) = data to be written into Subport (low nibble)
SPort_Data (hi) = data to be written into Subport (high nibble)
(Auxiliary Register Write)
Aux._Data Addr. (ASW) OUT
(Primary Register Write)
Addr. (M2) Addr. (ASW) OUT
Addr. (M2) Addr. (ASW) OUT
(Auxiliary Register Write Byte)
Addr. (M2) Addr. (ASW) OUT
Aux._Data (lo) Addr. (M2) OUT
Pirm._Data Addr. (M2) OUT
(Primary Register Read)
(Auxiliary Register Read)
Aux._Data (hi) Addr. (M2) OUT
6
Aux. Reg.
Dual Register Access
5
Module M2
Addr. (M2) IN
Addr. (M2) IN
Primary Reg.
4
to other modules
7
7
(Primary Register Write)
Prim._Data Address (M3) OUT
(Primary Register Read)
Single Register Access
Primary Reg.
Module M3
Address (M3) IN
7
4711B–4BMCU–01/05
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