XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 70

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

DS083 (v4.7) November 5, 2007
Product Specification
03/24/03
05/27/03
06/02/03
08/25/03
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10/14/03
12/10/03
02/19/04
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11/17/04
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09/15/05
Date
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Version
2.5.1
2.7.1
3.1.1
2.6
2.7
2.8
2.9
3.0
3.1
3.2
4.0
4.1
4.2
4.3
4.4
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Merged in DS110-2 (Module 2 of Virtex-II Pro X data sheet). Separate RocketIO and
RocketIO X sections created.
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No changes in Module 2 for this revision.
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Removed Compatible Output Standards and Compatible Input Standards tables.
Corrected sentence in section
optional weak-keeper circuit is connected to each user I/O pad.”
Added section
Added four Differential Termination I/O standards to
Added section
Added footnote referring to XAPP659 to 3.3V I/O callouts in
Section
Deleted section
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
Section
Recompiled for backward compatibility with Acrobat 4 and above. No content
Section
Reassigned heading hierarchies for better agreement with content.
Table
and SSTL18_II_DCI respectively.
Figure
Added new
Output
be held to a constant DC level during and after configuration.
page
Sections
"falling" edge with respect to DOUT.
Table 8, page 24
from 1.08V to 1.1V.
-5 and -6, are released to Production status.
to be I0 or I1. Corrected signal names in
CLK1 to I0 and I1.
changes.
clock feedback.
Figure 11, page
Section
standard in the first example from LVDS_25_DCI to LVDS_25.
Table
respectively.
Table
Table
Table
Table
Table
Xilinx 10G (Aurora) protocols.
Changed all instances of 10.3125 Gb/s to 6.25 Gb/s.
Table
encoding, 1.8V for all other encoding protocols.
10. Added section
10: Corrected I/O standard names SSTL18_I and SSTL18_II to SSTL18_I_DCI
7: Corrected VCCAUXTX and VCCAUXRX to AVCCAUXTX and AVCCAUXRX
9: Corrected V
25: Corrected SelectRAM+ memory available for XC2VPX70 device.
33: Updated configuration default bitstream lengths.
1: Deleted SONET OC-192 protocol.
3: Deleted RocketIO X primitives for SONET OC-192, 10 Gbit Ethernet, and
7: Changed RocketIO X VCCAUXRX from 1.5V globally to 1.5V for 8B/10B
61, text below: Corrected wording of criteria for clock switching.
Standards. This table replaces deleted I/O standards tables.
BUFGMUX, page
Configuration, page
Clock De-skew, page
Rules for Combining I/O Standards in the Same Bank, page
Slave-Serial Mode
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Table
Rules for Combining I/O Standards in the Same Bank, page
On-Chip Differential Termination
Functional Description: RocketIO Multi-Gigabit Transceiver (MGT),
12: Corrected figure by removing coupling capacitors from input.
and
12,
www.xilinx.com
OD
Summary of Voltage Supply Requirements for All Input and
Table 10, page
(output voltage) range for LVDSEXT_25.
Local Clocking, page
50: Corrected the definition of the "presently selected clock"
and
56: Added text indicating that the mode pins M0-M2 must
52: Removed reference to CLK2X as an option for DCM
Input/Output Individual Options, page
Master-Serial Mode, page
Revision
25: Corrected Input V
Figure 61
51.
and
and associated text from CLK0 and
Table 9
Figure 31, page
REF
56: Changed "rising" to
and
Table 8
for HSTL_III-IV_18
Table
and
29: Corrected I/O
27, to read “The
34.
12.
Table
Module 2 of 4
29.
12.
59