XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 114

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Table 52: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
2. These measurements include:
3. IFF = Input Flip-Flop or Latch
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in
Characteristics Standard Adjustments,
page
No Delay
Global Clock and IFF
relative to the Global Clock input signal with the slowest route and heaviest load.
-
-
23.
CLK0 and CLK180 DCM jitter
Worst-case duty-cycle distortion using CLK0 and CLK180, T
IOB Input Switching
(1)
R
Description
(2)
with DCM
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
PSDCM
Symbol
/T
PHDCM
www.xilinx.com
DCD_CLK180
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
.
1.54/–0.58
1.59/–0.59
1.66/–0.61
1.68/–0.53
1.68/–0.53
1.81/–0.74
1.85/–0.65
1.85/–0.57
1.86/–0.45
1.86/–0.45
N/A
-7
Speed Grade
1.54/–0.57
1.59/–0.58
1.66/–0.59
1.68/–0.53
1.81/–0.74
1.85/–0.64
1.85/–0.54
1.86/–0.39
1.86/–0.35
1.68/–0.53
1.86/–0.39
-6
1.54/–0.56
1.59/–0.57
1.66/–0.57
1.68/–0.50
1.68/–0.50
1.81/–0.71
1.85/–0.60
1.85/–0.50
1.86/–0.30
1.86/–0.30
1.87/–0.28
-5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43