XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 64

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Two separate components of the phase shift range must be
understood:
•
•
The
equation:
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in
FPGAs: DC and Switching
Absolute range (fixed mode) = ±
Absolute range (variable mode) = ±
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
Table 30: DCM Frequency Ranges
DS083 (v4.7) November 5, 2007
Product Specification
CLK0, CLK180
CLK90, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
PHASE_SHIFT
FINE_SHIFT_RANGE
Phase Shift (ns) = (
PHASE_SHIFT
Output Clock
FINE_SHIFT_RANGE
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
R
attribute range
attribute is the numerator in the following
Virtex-II Pro and Virtex-II Pro X Platform
PHASE_SHIFT
DCM timing parameter range
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
Characteristics.
component, which represents
CLKIN Input
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
CLKFB
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
Low-Frequency Mode
/256) * PERIOD
Figure 63: Fine-Phase Shifting Effects
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
(PS/256) x PERIOD CLKIN
(PS negative)
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_2X_LF
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_FX_LF
(PS/256) x PERIOD CLKIN
CLKIN
www.xilinx.com
CLK Output
(PS negative)
/2
since the
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
•
•
•
Operating Modes
The frequency ranges of DCM input and output clocks
depend
low-frequency mode or high-frequency mode, according to
Table
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics. The CLK2X, CLK2X180, CLK90, and CLK270 out-
puts are not available in high-frequency mode.
High or low-frequency mode is selected by an attribute.
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT
30. For actual values, see
PHASE_SHIFT
(PS/256) x PERIOD CLKIN
on
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
(PS positive)
(PS/256) x PERIOD CLKIN
CLKIN
CLKIN
CLKIN
CLKIN Input
the
is limited to
(PS positive)
NA
NA
= 2 *
=
≤ 0.5 *
fixed mode is limited to
fixed mode is limited to
operating
High-Frequency Mode
FINE_SHIFT_RANGE
value never changes after configu-
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
±
255 in either mode.
±
±
mode
64.
128.
CLKOUT_FREQ_1X_HF
CLKOUT_FREQ_DV_HF
CLKOUT_FREQ_FX_HF
DS031_48_110300
CLK Output
Virtex-II Pro and
specified,
, then
±
±
NA
NA
, then
128, and in
255, and in
Module 2 of 4
, then
either
53