XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 101

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
details.) The propagation delay of the 4" trace is character-
ized separately and subtracted from the final measurement,
and is therefore not included in the generalized test setup
shown in
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
inx.com/support/sw_ibis.htm
C
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
Table 37: Output Delay Measurement Methodology
DS083 (v4.7) November 5, 2007
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
REF
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
, and V
Figure
Virtex-II Pro Platform FPGA User Guide
R
MEAS
6.
fully describe the test conditions for each
Description
MEAS
.) Parameters V
.
Table
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
37.
http://support.xil-
REF
, R
www.xilinx.com
REF
for
,
PCI33_3 (falling edge)
PCI66_3 (falling edge)
PCI33_3 (rising edge)
PCI66_3 (rising edge)
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
PCIX (rising edge)
PCIX (falling edge
IOSTANDARD
HSTL_III_18
HSTL_IV_18
HSTL_II_18
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I_18
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table
delay (clock-to-input) of the PCB trace.
LVTTL (all)
Attribute
HSTL_IV
HSTL_III
HSTL_II
HSTL_I
GTLP
FPGA Output
GTL
35) to yield the actual worst-case propagation
Figure 6: Generalized Test Setup
V
MEAS
REF
R
(Ω)
1M
1M
1M
1M
R
C
(probe capacitance)
1M
25
25
25
25
25
25
25
25
50
25
25
50
25
50
25
50
REF
.
REF
REF
V
(voltage level at which
delay measurement is taken)
MEAS
C
(pF)
REF
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(2)
(2)
(2)
(2)
(3)
(3)
(1)
ds083-3_06a_092503
V
V
V
V
V
1.65
1.65
1.25
0.75
0.94
2.03
0.94
2.03
0.94
2.03
MEAS
(V)
0.9
1.1
0.9
0.8
1.0
0.9
1.1
REF
REF
REF
REF
Module 3 of 4
V
0.75
0.75
(V)
3.3
3.3
3.3
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
REF
0
0
0
0
0
0
0
0
30