XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 48

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

The set and reset functionality of a register or a latch can be
configured as follows:
•
•
•
•
•
•
•
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM+ Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous
SelectRAM+ element. SelectRAM+ elements are config-
urable within a CLB to implement the following:
•
•
•
DS083 (v4.7) November 5, 2007
Product Specification
CLK
Figure 35: Register / Latch Configuration in a Slice
CE
SR
BY
BX
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Single-Port 16 x 8-bit RAM
Single-Port 32 x 4-bit RAM
Single-Port 64 x 2-bit RAM
R
DX
RAM
DY
resource
D
CE
CK
D
CE
CK
SR REV
SR REV
called
FFY
FFX
FF
LATCH
FF
LATCH
Q
Q
a
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Attribute
Attribute
DS083-2_22_122001
Reset Type
distributed
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
SYNC
ASYNC
YQ
XQ
www.xilinx.com
Table 16: Distributed SelectRAM+ Configurations
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•
•
•
Distributed SelectRAM+ memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM+ memory and the storage element
share the same clock input. A Write Enable (WE) input is
active High, and is driven by the SR input.
Table 16
by each distributed SelectRAM+ configuration.
For single-port configurations, distributed SelectRAM+
memory has one address port for synchronous writes and
asynchronous reads.
For dual-port configurations, distributed SelectRAM+ mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
Notes:
1. S = single-port configuration; D = dual-port configuration
Single-Port 128 x 1-bit RAM
Dual-Port 16 x 4-bit RAM
Dual-Port 32 x 2-bit RAM
Dual-Port 64 x 1-bit RAM
shows the number of LUTs (2 per slice) occupied
128 x 1S
16 x 1D
32 x 1D
64 x 1D
16 x 1S
32 x 1S
64 x 1S
RAM
Number of LUTs
1
2
2
4
4
8
8
Module 2 of 4
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