CY7C1480BV25-167BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV25-167BZXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1480BV25-167BZXC
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 001-15143 Rev. *H
A
BW
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
V
V
V
V
Note
2. Applicable for TQFP package. For BGA package V
Pin Name
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
D
G
, BW
, BW
, BW
1
[2]
, A
B
H
E
, BW
, BW
C
F
,
,
I/O Power Supply Power Supply for the I/O Circuitry.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Ground
Ground
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
A0 are fed to the two-bit counter.
Byte Write Select (BWS) Inputs, Active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable (BWE) Input, Active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Captures all synchronous inputs to the device. Also increments the burst counter
when ADV is asserted LOW during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin must be LOW
or left floating. ZZ pin has an internal pull down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by the addresses presented during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQP
Power Supply Inputs to the Core of the Device.
Ground for the Core of the Device.
Ground for the I/O Circuitry.
SS
serves as ground for the core and the I/O circuitry.
1
1
2
and CE
and CE
and CE
2
3
3
to select or deselect the device. CE
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
X
CY7C1482BV25, CY7C1486BV25
are placed in a tristate condition.
Description
1
, CE
2
3
is sampled only when a new external
is sampled only when a new external
2
, and CE
1
is deasserted HIGH.
CY7C1480BV25
3
are sampled active. A1:
1
is HIGH. CE
X
Page 8 of 34
and BWE).
1
is
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