CY7C1480BV25-167BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV25-167BZXC Datasheet - Page 25

• Manufacturer Part Number: CY7C1480BV25-167BZXC
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Notes
Document Number: 001-15143 Rev. *H
23. On this diagram, when CE is LOW: CE
24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BW
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t CL
(continued)
t DS
Single WRITE
D(A1)
1
is LOW, CE
t ADH
t DH
A2
2
is HIGH, and CE
Figure 5. Write Cycle Timing
D(A2)
DON’T CARE
3
is LOW. When CE is HIGH: CE
D(A2 + 1)
t WES
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
X
LOW.
ADV suspends burst
CY7C1482BV25, CY7C1486BV25
[23, 24]
D(A2 + 2)
1
ADSC extends burst
is HIGH, CE
D(A2 + 3)
2
is LOW, or CE
t ADS
A3
D(A3)
t ADH
CY7C1480BV25
t
3
ADVS
t WES
is HIGH.
Extended BURST WRITE
D(A3 + 1)
t WEH
t
ADVH
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D(A3 + 2)
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