CY7C1480BV25-200AXC Cypress Semiconductor Corporation., CY7C1480BV25-200AXC Datasheet

CY7C1480BV25-200AXC

Manufacturer Part Number

CY7C1480BV25-200AXC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1480BV25-200AXC.pdf (31 pages)

2.CY7C1480BV25-200AXC.pdf (31 pages)

Specifications of CY7C1480BV25-200AXC

Package

QFP

Date_code

09+

Current page: 1 of 31
Download datasheet (469Kb)

Features

Selection Guide

Note

Cypress Semiconductor Corporation

Document #: 001-15143 Rev. *D

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

1. For best practices recommendations, refer to the Cypress application note

Supports bus operation up to 250 MHz

Available speed grades are 250, 200, and 167 MHz

Registered inputs and outputs for pipelined operation

2.5V core power supply

2.5V IO operation

Fast clock-to-output time

Provide high performance 3-1-1-1 access rate

User selectable burst counter supporting Intel

interleaved or linear burst sequences

Separate processor and controller address strobes

Synchronous self timed writes

Asynchronous output enable

Single cycle chip deselect

CY7C1480BV25, CY7C1482BV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1486BV25

available in Pb-free and non-Pb-free 209-ball FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

“ZZ” Sleep Mode option

3.0 ns (for 250 MHz device)

Description

•

198 Champion Court

Pentium

AN1064, SRAM System

72-Mbit (2M x 36/4M x 18/1M x 72)

Functional Description

The

SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE

Chip Enables (CE

ADSP, and ADV), Write Enables (BW

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) is active. Subsequent burst addresses

can be internally generated as controlled by the Advance pin

(ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed Write cycle. This part supports Byte Write

operations (see

page 10

bytes wide, as controlled by the byte write control inputs. When

it is active LOW, GW writes all bytes.

250 MHz

450

120

3.0

•

CY7C1482BV25, CY7C1486BV25

for further details). Write cycles can be one to two or four

CY7C1480BV25/CY7C1482BV25/CY7C1486BV25

San Jose

Guidelines.

“Pin Definitions” on page 7

200 MHz

450

120

3.0

and CE

Pipelined Sync SRAM

CA 95134-1709

), Burst Control inputs (ADSC,

167 MHz

CY7C1480BV25

Revised February 29, 2008

400

120

3.4

, and BWE), and Global

and

•

), depth-expansion

“Truth Table” on

408-943-2600

Unit

[1]

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