CY7C1480BV25-167BZXC CYPRESS [Cypress Semiconductor], CY7C1480BV25-167BZXC Datasheet - Page 21

• Manufacturer Part Number: CY7C1480BV25-167BZXC
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage on V
Supply voltage on V
DC voltage applied to outputs
in tristate ............................................–0.5 V to V
DC input voltage .................................. –0.5 V to V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch up current..................................................... > 200 mA
Operating Range
Electrical Characteristics
Over the Operating Range
Notes
Document Number: 001-15143 Rev. *H
Commercial
Industrial
V
V
V
V
V
V
I
I
I
13. Overshoot: V
14. Power up: assumes a linear ramp from 0 V to V
15. The operation current is calculated with 50% read cycle and 50% write cycle.
Parameter
X
OZ
DD
DD
DDQ
OH
OL
IH
IL
Range
[15]
Power supply voltage
I/O supply voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current except
ZZ and MODE
Input current of MODE
Input current of ZZ
Output leakage current
V
IH
–40 C to +85 C
DD
(AC) < V
0 C to +70 C
Temperature
operating supply current V
Ambient
DD
DDQ
Description
DD
relative to GND ........–0.3 V to +3.6 V
+ 1.5 V (pulse width less than t
relative to GND....... –0.3 V to +V
[13, 14]
[13]
[13]
2.5 V– 5% / + 5% 2.5 V – 5%
V
DD
DD
(min.) within 200 ms. During this time V
For 2.5 V I/O
For 2.5 V I/O, I
For 2.5 V I/O, I
For 2.5 V I/O
For 2.5 V I/O
GND  V
Input = V
Input = V
Input = V
Input = V
GND  V
f = f
DD
MAX
= Max, I
DDQ
CYC
DD
/2).Undershoot: V
= 1/t
I
SS
DD
SS
DD
I
+ 0.5 V
+ 0.5 V
to V
 V
 V
V
DDQ
OUT
CYC
DDQ
DDQ,
DD
DD
OH
OL
= 0 mA,
= 1.0 mA
= –1.0 mA
output disabled
Test Conditions
IL
(AC) > –2 V (pulse width less than t
Neutron Soft Error Immunity
LSBU
LMBU
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 
cation Note
Terrestrial Failure Rates”
Parameter
IH
< V
CY7C1482BV25, CY7C1486BV25
2
DD
, 95% confidence limit calculation. For more details refer to Appli-
AN 54908 “Accelerated Neutron SER Testing and Calculation of
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
and V
Description
Single event
single-bit
DDQ
multi-bit
latch up
Logical
Logical
upsets
upsets
< V
DD
.
CYC
/2).
Conditions
25 °C
25 °C
85 °C
Test
2.375
2.375
–0.3
Min
–30
CY7C1480BV25
2.0
1.7
–5
–5
–5
–
–
–
–
–
–
V
Typ Max* Unit
361
0
0
DD
2.625
Max
V
450
450
400
0.4
0.7
+ 0.3 V
30
–
5
–
5
–
5
DD
Page 21 of 34
0.01
394
0.1
FIT/
FIT/
FIT/
Dev
Unit
Mb
Mb
mA
mA
mA
A
A
A
A
A
A
V
V
V
V
V
V
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