CY7C1480BV25-200BZC Cypress Semiconductor Corp, CY7C1480BV25-200BZC Datasheet

Page 1

... Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1480BV25, CY7C1482BV25 available in ■ JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball fine pitch ball grid array (FBGA) package. CY7C1486BV25 available in Pb-free and non-Pb-free 209-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ...

Page 2

... Logic Block Diagram – CY7C1480BV25 ( A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C WRITE REGISTER BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1482BV25 (4M x 18) ...

Page 3

... WRITE DRIVER WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480BV25 OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP H INPUT ...

Page 4

... Boundary Scan Exit Order (1M x 72) ............................ 19 Maximum Ratings........................................................... 20 Operating Range ............................................................ 20 Electrical Characteristics .............................................. 20 Capacitance .................................................................... 21 Thermal Resistance ....................................................... 21 Switching Characteristics ............................................. 22 Switching Waveforms .................................................... 23 Ordering Information ..................................................... 27 Package Diagrams ......................................................... 28 Document History Page................................................. 31 Sales, Solutions, and Legal Information ...................... 31 Worldwide Sales and Design Support....................... 31 Products .................................................................... 31 PSoC Solutions ......................................................... 31 16 CY7C1480BV25 Page [+] Feedback [+] Feedback ...

Page 5

... Figure 1. 100-Pin TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ CY7C1482BV25 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1480BV25 DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ ( DDQ 60 V SSQ SSQ V 54 DDQ Page [+] Feedback [+] Feedback ...

Page 6

... D D DDQ DDQ DDQ DDQ N DQP DDQ MODE NC/288M NC/144M CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document Number: 001-15143 Rev. *F CY7C1482BV25, CY7C1486BV25 CY7C1480BV25 ( BWE CLK TDI A1 TDO TMS TCK CY7C1482BV25 ( BWE ...

Page 7

... G C NC/144M NC/576M BWS CE BWS NC/ DDQ DDQ DDQ DDQ DDQ DD DDQ DDQ DD DDQ DDQ DD DD DDQ DDQ DDQ MODE TDI CY7C1480BV25 BWS BWS BWS BWS DQP DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP DQP DDQ DDQ ...

Page 8

... ADSP is ignored and CE to select or deselect the device and CE to select or deselect the device are placed in a tristate condition. X serves as ground for the core and the I/O circuitry. SS CY7C1480BV25 , CE , and CE are sampled active. A1 and BWE HIGH sampled only when a new external 2 ...

Page 9

... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism is provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common I/O device, the Output Enable (OE) must deasserted HIGH before presenting data to the DQs inputs. ...

Page 10

... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tristates the output drivers safety precaution, DQs are automatically tristated whenever a write cycle is detected, regardless of the state of OE ...

Page 11

... Table 4. Truth Table The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows. Operation Add. Used Deselect cycle, power down None Deselect cycle, power down None Deselect cycle, power down None Deselect cycle, power down None Deselect cycle, power down None Sleep mode, power down ...

Page 12

... Table 5. Truth Table for Read/Write The read-write truth table for the CY7C1480BV25 follows. Function (CY7C1480BV25) Read Read Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ) B B Write bytes B, A Write byte C – (DQ and DQP ) C C Write bytes C, A Write bytes C, B Write bytes Write byte D – ...

Page 13

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incor- porates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...

Page 14

... SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a CY7C1480BV25 Page [+] Feedback [+] Feedback ...

Page 15

... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED Description / ns CY7C1480BV25 TDOV t TDOX Min Max Unit 50 – ns – 20 MHz 20 – – ns – – ...

Page 16

... GND ≤ V ≤ DDQ CY7C1482BV25 CY7C1486BV25 (4M x 18) (1M x72) 000 000 01011 01011 000000 000000 010100 110100 00000110100 00000110100 1 1 Bit Size (x36 – CY7C1480BV25 1.25V 50Ω 50Ω 20pF O Min Max Unit 1.7 – V 2.1 – V – 0.4 V – 0 – ...

Page 17

... J11 P6 44 K10 R6 45 J10 N6 46 H11 P11 47 G11 R8 48 F11 P3 49 E11 P4 50 D10 P8 51 D11 P9 52 C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 CY7C1480BV25 Bit # 165-Ball Page [+] Feedback [+] Feedback ...

Page 18

... Boundary Scan Exit Order (4M x 18) Bit # 165-Ball P11 Document Number: 001-15143 Rev. *F CY7C1482BV25, CY7C1486BV25 Bit # 165-Ball P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480BV25 Bit # 165-Ball ID 37 C11 38 A11 39 A10 40 B10 Page [+] Feedback [+] Feedback ...

Page 19

... L11 W6 71 L10 J11 V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480BV25 Bit # 209-Ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 100 A8 101 B4 102 B3 103 C3 104 C4 ...

Page 20

... MAX CYC 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz /2).Undershoot: V (AC) > –2 V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480BV25 Test Description Typ Max* Unit Conditions Logical 25 °C 361 394 single-bit upsets Logical 25 °C 0 ...

Page 21

... EIA/JESD51. Figure 6. AC Test Loads and Waveforms R = 1667Ω 2 OUTPUT DDQ GND 1583Ω INCLUDING JIG AND (b) SCOPE CY7C1480BV25 Min Max 200 200 200 120 200 200 200 135 165 FBGA 209 FBGA Package Package 6 ...

Page 22

... Test Loads and Waveforms” on page is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1480BV25 “AC Test Loads and 200 MHz 167 MHz Max Min Max Min Max ...

Page 23

... OEV OEHZ t OELZ t DOH Q(A2 Q(A1) DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1480BV25 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH. ...

Page 24

... CY7C1482BV25, CY7C1486BV25 [19, 20] 8. Figure 8. Write Cycle Timing A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1480BV25 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE Page [+] Feedback ...

Page 25

... The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 22 HIGH. Document Number: 001-15143 Rev. *F CY7C1482BV25, CY7C1486BV25 [19, 21, 22] Figure 9. Figure 9. Read/Write Cycle Timing WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED CY7C1480BV25 A5 A6 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page [+] Feedback [+] Feedback ...

Page 26

... DQs are in high-Z when exiting ZZ sleep mode. Document Number: 001-15143 Rev. *F CY7C1482BV25, CY7C1486BV25 [23, 24] Figure 10. ZZ Mode Timing DDZZ High-Z DON’T CARE “Truth Table” on page 11 for all possible signal conditions to deselect the device. CY7C1480BV25 t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback [+] Feedback ...

Page 27

... Speed Package (MHz) Ordering Code Diagram 167 CY7C1480BV25-167AXC 51-85050 100-pin TQFP ( 1.4 mm) Pb-free CY7C1480BV25-167BZXC 51-85165 165-ball FBGA ( 1.4 mm) Pb-free 200 CY7C1480BV25-200BZC 51-85165 165-ball FBGA ( 1.4 mm) 250 CY7C1480BV25-250BZI 51-85165 165-ball FBGA ( 1.4 mm) Ordering Code Definition 14XX B V25 - XXX BZ ( Document Number: 001-15143 Rev. *F CY7C1482BV25, CY7C1486BV25 www ...

Page 28

... Package Diagrams Figure 11. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm), 51-85050 Document Number: 001-15143 Rev. *F CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 51-85050 *C Page [+] Feedback [+] Feedback ...

Page 29

... Package Diagrams (continued) Figure 12. 165-Ball FBGA ( 1.4 mm), 51-85165 Document Number: 001-15143 Rev. *F CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 51-85165 *B Page [+] Feedback [+] Feedback ...

Page 30

... Logical Multi Bit Upset SEL Single Event Latch Up TDO Test Data Out TCK Test Clock TDI Test Data In TMS Test Mode Select TAP Test Access Port TQFP thin quad flatpack Document Number: 001-15143 Rev. *F CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 51-85167 *A Page [+] Feedback [+] Feedback ...

Page 31

... Document History Page Document Title: CY7C1480BV25/CY7C1482BV25/CY7C1486BV25, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 001-15143 Submission REV. ECN NO. Date ** 1024385 See ECN VKN/KKVTMP New Data Sheet *A 1562944 See ECN *B 1897447 See ECN *C 2082487 See ECN *D 2159486 See ECN *E 2899725 ...