CY7C1480BV25-167AXI CYPRESS [Cypress Semiconductor], CY7C1480BV25-167AXI Datasheet
CY7C1480BV25-167AXI
Related parts for CY7C1480BV25-167AXI
CY7C1480BV25-167AXI Summary of contents
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... Synchronous self timed writes ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1480BV25, CY7C1482BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1486BV25 available in Pb-free and non-Pb-free 209-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ...
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... Logic Block Diagram – CY7C1480BV25 ( A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C WRITE REGISTER BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE ...
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... WRITE DRIVER WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480BV25 OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP H INPUT ...
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... DQ A DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1480BV25 DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ ...
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... DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document #: 001-15143 Rev. *D CY7C1482BV25, CY7C1486BV25 CY7C1480BV25 ( BWE CLK ...
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... DD DDQ DDQ DD DDQ MODE TDI CY7C1480BV25 BWS BWS BWS BWS DQP DQP ...
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... CE to select or deselect the device and CE to select or deselect the device are placed in a tri-state condition. X serves as ground for the core and the IO circuitry. SS CY7C1480BV25 , CE , and CE are sampled active. A1 and BWE HIGH sampled only when a new external ...
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... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism is provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common IO device, the Output Enable (OE) must deasserted HIGH before presenting data to the DQs inputs. ...
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... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE ...
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... Table 4. Truth Table The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows. Operation Add. Used Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Sleep Mode, Power Down ...
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... Table 5. Truth Table for Read/Write The read-write truth table for the CY7C1480BV25 follows. Function (CY7C1480BV25) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incor- porates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a CY7C1480BV25 Page [+] Feedback ...
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... These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED Description / ns CY7C1480BV25 TDOV t TDOX Min Max Unit MHz ...
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... GND ≤ V ≤ DDQ CY7C1482BV25 CY7C1486BV25 (4M x 18) (1M x72) 000 000 01011 01011 000000 000000 010100 110100 00000110100 00000110100 1 1 Bit Size (x36 CY7C1480BV25 1.25V 50Ω 50Ω 20pF O Min Max Unit 1.7 V 2.1 V 0.4 V 0 –0.3 0.7 V μA –5 ...
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... P4 50 D10 P8 51 D11 P9 52 C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 CY7C1480BV25 Bit # 165-Ball Page [+] Feedback ...
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... P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480BV25 Bit # 165-Ball ID 37 C11 38 A11 39 A10 40 B10 ...
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... V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480BV25 Bit # 209-Ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 ...
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... /2).Undershoot: V (AC) > –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480BV25 + 0.5V DD Ambient Temperature 0°C to +70°C 2.5V –5%/+5% 2.5V– –40°C to +85°C Min Max 2.375 2.625 2 ...
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... Max Test conditions follow 24.63 standard test methods and procedures for measuring 2.28 thermal impedance, per EIA/JESD51 1667Ω 2.5V V OUTPUT DDQ GND 1583Ω INCLUDING JIG AND (b) SCOPE CY7C1480BV25 165 FBGA 209 FBGA Unit Package Package ...
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... Test Loads and Waveforms” on page is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1480BV25 “AC Test Loads and 200 MHz 167 MHz Max Min Max Min Max ...
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... OEV OEHZ t OELZ t DOH Q(A2 Q(A1) DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1480BV25 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... Document #: 001-15143 Rev. *D CY7C1482BV25, CY7C1486BV25 [19, 20] 7. Figure 7. Write Cycle Timing A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1480BV25 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 22 HIGH. Document #: 001-15143 Rev. *D CY7C1482BV25, CY7C1486BV25 [19, 21, 22] Figure 8. Figure 8. Read/Write Cycle Timing WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED CY7C1480BV25 A5 A6 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page [+] Feedback ...
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... DQs are in high-Z when exiting ZZ sleep mode. Document #: 001-15143 Rev. *D CY7C1482BV25, CY7C1486BV25 [23, 24] Figure 9. ZZ Mode Timing DDZZ High-Z DON’T CARE “Truth Table” on page 10 for all possible signal conditions to deselect the device. CY7C1480BV25 t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1482BV25-167BZXC CY7C1486BV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1486BV25-167BGXC CY7C1480BV25-167AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1482BV25-167AXI CY7C1480BV25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) ...
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... Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1482BV25-250AXI CY7C1480BV25-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1482BV25-250BZI CY7C1480BV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1482BV25-250BZXI CY7C1486BV25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1486BV25-250BGXI Document #: 001-15143 Rev ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1480BV25 1.40±0.05 12°±1° A SEE DETAIL (8X) ...
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... SEATING PLANE C Document #: 001-15143 Rev. *D CY7C1482BV25, CY7C1486BV25 0.15(4X) CY7C1480BV25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 51-85165-*A Page ...
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... Package Diagrams (continued) Figure 12. 209-Ball FBGA ( 1.76 mm), 51-85167 Document #: 001-15143 Rev. *D CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 51-85167-** Page [+] Feedback ...
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... Document History Page Document Title: CY7C1480BV25/CY7C1482BV25/CY7C1486BV25, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 001-15143 Orig. of REV. ECN NO. Issue Date Change ** 1024385 See ECN VKN/KKVTMP New Data Sheet *A 1562944 See ECN VKN/AESA *B 1897447 See ECN VKN/AESA *C 2082487 See ECN *D 2159486 See ECN VKN/PYRS © ...