CY7C1470BV25_11 CYPRESS [Cypress Semiconductor], CY7C1470BV25_11 Datasheet - Page 23

• Manufacturer Part Number: CY7C1470BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 3
Figure 4
Notes
Document Number: 001-15032 Rev. *I
27. For this waveform ZZ is tied LOW.
28. When CE is LOW, CE
29. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
30. Device must be deselected when entering ZZ mode. See
31. IOs are in High Z when exiting ZZ sleep mode.
In-Out (DQ)
ADDRESS
ADV/LD
shows NOP, STALL and DESELECT Cycles waveform.
shows ZZ Mode timing waveform.
BWx
Data
CEN
CLK
WE
CE
A LL INPUTS
(except ZZ)
Outputs (Q)
WRITE
D(A1)
I
1
A1
1
SUPPLY
is LOW, CE
CLK
ZZ
READ
Q(A2)
A2
2
2
(continued)
is HIGH, and CE
t
ZZI
STALL
Figure 3. NOP, STALL and DESELECT Cycles
t
I
ZZ
DDZZ
3
[30, 31]
3
is LOW. When CE is HIGH,CE
Truth Table on page 10
D(A1)
Figure 4. ZZ Mode Timing
Q(A3)
READ
A3
4
Q(A2)
WRITE
D(A4)
DON’T CARE
[27, 28, 29]
A4
DON’T CARE
5
for all possible signal conditions to deselect the device.
High-Z
1
is HIGH, CE
STALL
6
CY7C1472BV25, CY7C1474BV25
Q(A3)
2
is LOW, or CE
UNDEFINED
NOP
7
DESELECT or READ Only
t RZZI
3
is HIGH.
Q(A5)
D(A4)
READ
t
ZZREC
A5
8
CY7C1470BV25
DESELECT
9
CONTINUE
DESELECT
Page 23 of 29
Q(A5)
10
t
CHZ
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